Skip to main content
Department of Information Technology

This page is a copy of research/computer_systems/seminars/200604 (Wed, 31 Aug 2022 10:12:46)

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors

Authors
Mehdi Alipour (now at Ericsson), Stefanos Kaxiras, Rakesh Kumar (NTNU), and David Black-Schaffer (presenter)

Date and Time
June 4th 2020, 15:00 - 16:00

Location
Zoom: https://uu-se.zoom.us/j/61827085769

Abstract
Flexible instruction scheduling is essential for performance in out-of-order processors. This is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete flexibility in choosing ready instructions for execution, but at the cost of significant scheduling energy.

In this work we seek to reduce the instruction scheduling energy by reducing the depth and width of the IQ. We do so by classifying instructions based on their readiness and criticality, and using this information to bypass the IQ for instructions that will not benefit from its expensive scheduling structures and delay instructions that will not harm performance. Combined, these approaches allow us to offload a significant portion of the instructions from the IQ to much cheaper FIFO-based scheduling structures without hurting performance. As a result we can reduce the IQ depth and width by half, thereby saving energy.

Our design, Delay and Bypass (DNB), is the first design to explicitly address both readiness and criticality to reduce scheduling energy. By handling both classes we are able to achieve 95% of the baseline out-of-order performance while only using 33% of the scheduling energy. This represents a significant improvement over previous designs which addressed only criticality or readiness (91%/89% performance at 74%/53% energy).

Back to the seminar page

Updated  2022-08-31 10:12:46 by Victor Kuismin.