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You'll need to write an extra report about microprocessors or perform an extra lab on your own for MN2 (and thus get more points).
SC means that there is ONE global interleaving of accesses from both threads that everybody agrees on.
One such interlerleaving could be
1: A := 1
2: B := 1
1: if (B == 0) ...
2: if (A == 0) ...
In that case, none of the threads will declare success
x86 guarantees causal correctness, i.e., if an obesevation of an event A causes event B to happen, A will be globally ordered before B (see the "What value will get printed slide". x86 will guarantee that "1" will always get printed. However, there is no global order between stores made by different processors, i.e., there is not a global store order like the one in TSO.