CoDeR-MP

Funded by SSF, the Swedish Foundation for Strategic Research, 2009-2014.

Summary of Research
Embedded computer systems that must perform demanding computations under tight timing and resource constraints are ubiquitous in critical products of Swedish industry in many important sectors. Staying competitive by making software more sophisticated while limiting hardware costs, this industry now faces a paradigm shift, by the move to parallel multicore computer platforms, which offers drastic advantages over previous platforms, but also comes with new challenges for software and system design and maintenance. These challenges range from the development of new parallel algorithms for control and signal processing, via mapping and scheduling of computations on processor cores, to management of shared hardware resources such as caches and communication media. Thus prediction of system performance, latencies, and resource utilization in real-time multicore systems becomes a much harder task than that for single core ones. CoDeR-MP is a multi-disciplinary effort where researchers from computer science and control engineering team up in order to provide key technological solutions for developing, migrating, and maintaining embedded systems with high computational demand under real time and resource constraints. Within a holistic methodology, CoDeR-MP will address challenges in

• parallel algorithms for computationally demanding control and signal processing methods,
• mapping and scheduling of computations and communication between the above algorithms executed on several processor cores under performance, real-time, and resource constraints, and
• analysis and management of shared resources such as caches and inter-core communication devices.

CoDeR-MP will also provide techniques for adapting the above solutions to each other and to a given platform, as well as integrating them to support predictability, design space exploration, identification of bottle-necks, and maintainability of system design across layers of system hierarchy. As driver for and evaluator of research results, the developed technology will be used in the development of a future and migration of an existing embedded real-time industrial application to a multicore platform.

Publications

Project leader
Wang Yi

Faculty
Erik Hagersten (Performance Analysis)
Bengt Jonsson (Component Modelling and Analysis)
Alexander Medvedev (Parallel Signal Processing and Control)
Wang Yi (Resource Allocation & Timing Analysis)

PhD Students
Pontus Ekberg
David Eklöv
Nan Guan
Jonatan Linden
Olov Rosen
Andreas Sembrant
Andreas Sandberg
Martin Stigge
Pan Xiaoyue

Participating Companies:
ABB Robotics
ABB Corporate Research
SAAB Systems