Department of Information Technology
Uppsala Architecture Research Team
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Hardware Optimization

optimize.png Our hardware optimizations focus on improving efficiency by reducing power consumption and increasing performance and scalability in the memory system.

VIPS Directoryless Snoopless Scalable Memory Coherence

VIPS is a very simple, practically costless, invalidation-less, directory-less, snoop-less, coherence protocol for improved scalability and efficiency.

 VIPS coherence improvements in performance, energy, and area.

Energy-efficient Caches

By combining TLB and way information in an enhanced eTLB we can reduce power and improve performance for private caches.

 Dynamic energy reduction with a tag-less cache versus a standard VIPT cache.

Updated  2014-10-31 10:46:28 by Andreas Sembrant.