Department of Information Technology

Uppsala Architecture Research Team Publications

2014

2013

2012

2011

2010

Older Publications

Clicking on titles below takes you to a page with the abstract and/or links to the report. The corresponding BibTeX file is also available, as well as a preformatted list in Postscript and PDF formats.

Please respect the copyrights. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage. To copy otherwise, or to republish, requires a fee and/or specific permission of the authors and/or ACM/IEEE.

2006

  • STATSHARE: A Statistical Model for Managing Cache Sharing via Decay by Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, and Erik Hagersten. In 2006th Workshop on Modeling, Benchmarking and Simulation held in conjunction: with the 33rd Annual International Symposium on Computer Architecture, Boston, MA USA, June 2006, 2006.
  • Modeling Cache Sharing on Chip Multiprocessor Architectures by Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Erik Hagersten, and Stefanos Kaxiras. In Proceedings of the 2006 IEEE International Symposium of Workload Characterization: San Jose, California, USA, 2006.
  • Memory System Behavior of Java-Based Middleware by Martin Karlsson, Kevin E. Moorez, Erik Hagersten, and David A. Wood. In Hans Hansson, editor, ARTES - A network for Real-Time research and graduate Education in Sweden 1997-2006, volume 2006-006 of Technical reports from the Department of Information Technology, Uppsala University, The Department of Information Technology, Uppsala, p 830, 2006.
  • TMA: A Trap-Based Memory Architecture by Håkan Zeffer, Zoran Radovic, Martin Karlsson, and Erik Hagersten. In Proceedings of the 20th ACM International Conference on Supercomputing (ICS 2006), Cairns, Queensland, Australia, June 2006.
  • Exploiting Locality: A Flexible DSM Approach by Håkan Zeffer, Zoran Radovic, and Erik Hagersten. In Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2006), Rhodes Island, Greece, April 2006.
  • A Statistical Multiprocessor Cache Model by Erik Berg, Håkan Zeffer, and Erik Hagersten. In Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, Texas, USA, March 2006.

2005

  • Vasa: A Simulator Infrastructure with Adjustable Fidelity by Dan Wallin, Håkan Zeffer, Martin Karlsson, and Erik Hagersten. In Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2005), Phoenix, Arizona, USA, November 2005.
  • TMA: A Trap-Based Memory Architecture by Håkan Zeffer, Zoran Radovic, Martin Karlsson, and Erik Hagersten. Technical report 2005-015, Department of Information Technology, Uppsala University, May 2005.
  • Flexibility Implies Performance by Håkan Zeffer, Zoran Radovic, and Erik Hagersten. Technical report 2005-013, Department of Information Technology, Uppsala University, April 2005.

2004

2003

  • Memory System Behavior of Java-Based Middleware by Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood. In Proceedings of the Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, California, USA, February 2003.

2002

  • Memory Characterization of the ECperf Benchmark by Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood. In Proceedings of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA29), Anchorage, Alaska, USA, May 2002.
  • RH Lock: A Scalable Hierarchical Spin Lock by Zoran Radovic and Erik Hagersten. In Proceedings of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA29), Anchorage, Alaska, USA, May 2002.

2001

  • Timestamp-Based Selective Cache Allocation by Martin Karlsson and Erik Hagersten. In High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003. Also published in Proceedings of the Workshop on Memory Performance Issues (WMPI 2001), held in conjunction with the 28th International Symposium on Computer Architecture (ISCA28), Göteborg, Sweden, June 2001.

2000

1999

  • WildFire: A Scalable Path for SMPs by Erik Hagersten and Michael Koster. In Proceedings of the 5th International Symposium on High-Performance Computer Architecture (HPCA-5), pages 172--181, Orlando, Florida, USA, January 1999.

Some of Erik's Old Papers

Complete list can be found here.

  • Gigaplane: A High Performance Bus for Large SMPs by Ashok Singhal, David Broniarczyk, Frederick Cerauskis, Jeff Price, Leo Yuan, Chris Cheng, Drew Doblar, Steve Fosth, Nalini Agarwal, Kenneth Harvey, and Erik Hagersten. In Proceedings of the IEEE Hot Interconnect IV, pages 41--52, Stanford University, August 1996.
  • Simple COMA Node Implementations by Erik Hagersten, Ashley Saulsbury, and Anders Landin. In Proceedings of the Hawaii International Conference on System Sciences (HICSS), January 1994. (The original Simple COMA paper.)
  • Simulating the Data Diffusion Machine by Erik Hagersten, Mats Grindal, Anders Landin, Ashley Saulsbury, Bengt Werner, and Seif Haridi. In Proceedings of the Parallel Architecture and Languages Europe (PARLE=EUROPAR), Springer-Verlag, June 1993. (Best Presentation Award.)
Updated  2015-08-20 13:54:41 by Magnus Själander.