Real-Time Systems are computer systems with constraints on the timing of actions. To ease the development and maintenance of application software, Real-time Systems often make use of a Real-Time Operating System (RTOS). Its main task is scheduling of application processes (tasks). Other functions can be inter process communication, interrupt handling, memory management etc.
Sometimes it is hard (or even impossible) to meet the time constraints specified for a real-time system, resulting in an incorrectly functioning application. A possible remedy is to redesign the system by upgrading the processor and/or remove functionality, etc. An alternative solution could be the use of a special purpose hardware accelerated RTOS. The aim of such an accelerator is to speedup RTOS functions that impose big overhead i.e. to reduce the kernel overhead by offloading the application processor. Accordingly, the processor gets more time for executing application software, and hopefully the time constraints can be met. The main drawback is the cost of extra hardware.
This thesis presents results from implementing RTOS functions in hardware, especially inter process communication (IPC) functions. The types of systems considered are uniprocessor and shared memory multiprocessor real-time systems.
IPC is used in systems with co-operating processes. The operating systems on the market support a large variation of IPC mechanisms. We will here present and evaluate three different IPC implementations. The first is an extended message queue mechanism that is used in commercial robot control applications. The second is the signal mechanism in OSE, a commercial RTOS predominantly used in telecommunication control applications, and the third is the semaphore and message queue mechanisms supported by the leading commercial RTOS VxWorks. All the implementations are based on a pre-emptive priority-based hardware real-time kernel accelerator.
We show that it is not optimal, practical or desirable to implement every kernel function into hardware, regarding systems in the scope of this thesis. However, an accelerator allows new functionality to be implemented. We illustrate this by implementing a message queue mechanism that supports priority inheritance for message arrival in hardware, which is too expensive to implement in software. Also, we show that substantial speedups are possible, and that a crucial mechanism in achieving speedup is the accelerator-processor interconnect. We further note that application speedups are possible, even in cases with an IPC-mechanism slow-down. The main reasons for this is that the accelerator can off-load the processor by handling the RTOS timing mechanism (clock-ticks), reducing the RTOS code to be executed on the processor, and handling interrupts.
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