@PhDThesis{	  itlic:2003-009,
  author	= {Martin Karlsson},
  title		= {Cache Memory Design Trade-offs for Current and Emerging
		  Workloads},
  school	= {Department of Information Technology, Uppsala University},
  department	= {Division of Computer Systems},
  year		= {2003},
  number	= {2003-009},
  type		= {Licentiate thesis},
  month		= sep,
  abstract	= {The memory system is the key to performance in
		  contemporary computer systems. When designing a new memory
		  system, architectural decisions are often arbitrated based
		  on their expected performance effect. It is therefore very
		  important to make performance estimates based on workloads
		  that accurately reflect the future use of the system. This
		  thesis presents the first memory system characterization
		  study of Java-based middleware, which is an emerging
		  workload likely to be an important design consideration for
		  next generation processors and servers.
		  
		  Manufacturing technology has reached a point where it is
		  now possible to fit multiple full-scale processors and
		  integrate board-level features on a chip. The raised
		  competition for chip resources has increased the need to
		  design more effective caches without trading off area or
		  power. Two common ways to improve cache performance is to
		  increase the size or associativity of the cache. Both of
		  these approaches come at a high cost in chip area as well
		  as power.
		  
		  This thesis presents two new cache organizations, each
		  aimed at more efficient use of either power or area. First,
		  the Elbow cache is presented, which is shown to be a
		  power-efficient alternative to highly set-associative
		  caches. Secondly, a selective cache allocation algorithm is
		  presented, RASCAL, that significantly reduces the miss
		  ratio at a limited cost in area.}
}