@TechReport{	  it:2012-013,
  author	= {Philip Axer and Rolf Ernst and Heiko Falk and Alain
		  Girault and Daniel Grund and Nan Guan and Bengt Jonsson and
		  Peter Marwedel and Jan Reineke and Christine Rochange and
		  Maurice Sebastian and von Hanxleden, Reinhard and Reinhard
		  Wilhelm and Wang Yi},
  title		= {Building Timing Predictable Embedded Systems},
  institution	= {Department of Information Technology, Uppsala University},
  department	= {Division of Computer Systems},
  year		= {2012},
  number	= {2012-013},
  month		= jul,
  abstract	= {A large class of embedded systems is distinguished from
		  general purpose computing systems by the need to satisfy
		  strict requirements on timing, often under constraints on
		  available resources. Predictable system design is concerned
		  with the challenge of building systems for which timing
		  requirements can be guaranteed a priori. Perhaps
		  paradoxically, this problem has become more difficult by
		  the introduction of performance-enhancing architectural
		  elements, such as caches, pipelines, and multithreading,
		  which introduce a large degree of nondeterminism and make
		  guarantees harder to provide. The intention of this paper
		  is to summarize current state-of-the-art in research
		  concerning how to build predictable yet performant systems.
		  We suggest precise definitions for the concept of
		  ``predictability'', and present predictability concerns at
		  different abstractions levels in embedded software design.
		  First, we consider timing predictability of processor
		  instruction sets. Thereafter, We consider how programming
		  languages can be equipped with predictable timing
		  semantics, covering both a language-based approach based on
		  the synchronous paradigm, as well as an environment that
		  provides timing semantics for a mainstream programming
		  language (in this case C). We present techniques for
		  achieving timing predictability on multicores. Finally we
		  discuss how to handle predictability at the level of
		  networked embedded systems, where randomly occurring errors
		  must be considered.}
}