Improving Processor Efficiency by Statically Pipelining Instructions
David Whalley E.P. Miles Professor, Florida State University
Date and Time
Monday, May 20th, 2013 at 11:15.
Polacksbacken, room 1212
A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. We describe the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.
About the speaker
David Whalley received his PhD in CS from the University of Virginia in 1990. He is the E.P. Miles professor in the Computer Science Department at Florida State University (FSU), an FSU Distinguished Research Professor, a Distinguished Member of the ACM, and an affiliated professor in the Computer Science & Engineering Department at Chalmers University of Technology.
His research interests include low-level compiler optimizations, tools for supporting the development and maintenance of compilers, program performance evaluation tools, predicting execution time, computer architecture, and embedded systems. More information about his background and research can be found on his homepage.