Senior Lecturer/Associate Professor at Department of Information Technology, Division of Computer Systems
- Visiting address:
- hus 10, Lägerhyddsvägen 1
- Postal address:
- Box 337
751 05 UPPSALA
Please visit my new webpage at the University of Murcia, Spain.
My research interests include compile-time and runtime code analysis and transformation, optimizations for performance and energy efficiency and software-hardware co-designs. I work on compiler techniques to achieve new levels of performance and energy efficiency (a decoupled access-execute model also available open source DAEDAL), and on the interaction between compiler and hardware (a compiler-assisted cache coherence protocol).
Keywords: compile-time code analysis optimizations parallel programming software-hardware co-designs energy efficiency performance
Currently I am a Ramon y Cajal researcher at the University of Murcia, Spain and affiliated Associate Professor at Uppsala University.
I received my Bachelor degree in Computer Science, from Babes-Bolyai University, Cluj-Napoca, Romania (ranked 1st with maximal grades throughout the degree - First Class Honours Degree), in 2008, followed by a Master degree in Computer Science, from Johannes-Keppler University, Linz, Austria, in 2009. I pursued my PhD studies in France researching in the area of automatic parallelization, by adapting the polyhedral model for dynamic thread level speculation (TLS), and I received the Doctoral degree in Computer Science, from the University of Strasbourg, France in 2012 (Advisors Ph. Clauss and V. Loechner). Next, I was a postdoctoral fellow at Uppsala University, Sweden (2012 - 2014) within UPMARC, a researcher (forskare) in UART, Uppsala University (2014 - 2015), continued as Assistant Professor (2015 - 2018), became Docent in Computer Science with specialization in compilers in 2018 and Associate Professor (since 2019). I was a visiting researcher at the University of Murcia, Spain (April-July 2015, 2016, and 2017), funded by competitive mobility grants.
News: I was granted a Ramon y Cajal grant and transitioned to the University of Murcia, Spain in May 2020.
I was granted a VR starting grant (Etableringsbidrag) of 3.4 MSEK for my project "Optimizing for performance and energy efficiency with speculative compilers and co-designed hardware" (2017-2020).
Publications from prior affiliations are available here. Please check my DBLP and Google Scholar for an up-to-date list.
I had the chance to work closely with a very good team of undergraduate and graduate students that contributed to the projects decoupled access-execute, the suite of compiler-assisted cache coherence protocols, and software-hardware co-designed optimizations:
Ph.D., Marina Schimchenko, Uppsala University: Optimizing for performance and energy efficiency with speculative compilers and co-designed hardware (main advisor, co-advisors Alberto Ros, Stefanos Kaxiras)
Ph.D., Kim-Anh Tran, Uppsala University: Compile-time analysis and optimizations for power efficient architectures (main advisor, co-advisor Stefanos Kaxiras) - graduated in 2020
Ph.D., Per Ekemark, Uppsala University: Towards Large-Scale, Distributed, Persistent Memory Systems (co-advisor, main advisor Stefanos Kaxiras, co-advisors Konstantinos Sagonas, Alberto Ros)
Ph.D., Christos Sakalis, Uppsala University: Software-hardware co-design with a focus on approximate computing (co-advisor, main advisor Magnus Sjalander) - graduated in 2021
Ph.D., Gustaf Borgstro?m, Uppsala University: Cache simulation methods (co-advisor, main advisor: David Black-Schaffer)
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