Uppsala Architecture Research Team
Hardware Optimization
Our hardware optimizations focus on improving efficiency by reducing power consumption and increasing performance and scalability in the memory system.
VIPS Directoryless Snoopless Scalable Memory Coherence
VIPS is a very simple, practically costless, invalidation-less, directory-less, snoop-less, coherence protocol for improved scalability and efficiency. |
Energy-efficient Caches
By combining TLB and way information in an enhanced eTLB we can reduce power and improve performance for private caches. |