Department of Information Technology
Uppsala Architecture Research Team

Previous Projects

Within this research project we explore the use of complete system simulation for analyzing high performance systems with quality of service requirements. By using Simics, a system-level instruction set simulator, operating systems and time sensitive applications may be analyzed without intrusion. Our goal is to develop tools and methods for performance analysis and debugging of complex real-time systems, using simulation as a building block. The research project is a subproject of the PAMP project.

Software-implementations of shared memory are still far behind the performance of hardware-based shared memory implementations and are not viable options for most fine-grain shared-memory applications. The major source for their inefficiency comes from the cost of interrupt-based asynchronous protocol processing, not from the actual network latency. As the raw hardware latency of inter-node communication decreases, the asynchronous overhead in the communication becomes more dominant. This project demonstrates how all the asynchronous overhead can be completely removed by running the entire coherence protocol in the requesting processor. This not only removes the asynchronous overhead, but also makes use of a processor that otherwise most likely would be stalled. The DSZOOM research is supported by Sun Microsystems, Inc. and Parallel and Scientific Computing Institute (PSCI).

The RASCAL Project

As processor technology reaches multi-gigaherz clock frequencies and several processor cores are put on the same die (CMP) the pressure on the memory subsystem, in terms of space and access time, increases dramatically. The RASCAL project addresses this issue by optimizing the memory system at the cache level, through selective cache allocation. The RASCAL algorithm detects data that requires extended caching at runtime and filter out the data that only requires short-term caching. The idea is not to allow data that is only accessed a few times to evict more important long-term data. Thereby allowing larger working sets to be kept in the cache. The RASCAL research is financed by SSF in the PAMP/ARTES program.

Scalable synchronization algorithms (RH lock and HBO locks) for Nonuniform Communication Architectures (NUCAs), such as CC-NUMAs built from a few large nodes or from chip multiprocessors (CMPs). This research is supported by Sun Microsystems, Inc. and Parallel and Scientific Computing Institute (PSCI).

SIP: Source Interdependence Profiling
Updated  2013-07-05 14:30:34 by David Black-Schaffer.