Uppsala Architecture Research Team
The Uppsala Architecture Research Team (UART) undertakes world-leading computer architecture research in measurement, modeling, and hardware and software optimization, with a focus on power and performance. Our approach starts with low-overhead measurement of key application and hardware data (typically on commodity hardware and often in an architecturally-independent manner). We then use this data to develop fast models for predicting performance, efficiency, and scalability across a range of systems and configurations. These models give us insight into application and hardware behavior, which allows us to develop targeted optimizations and new techniques to improve power and performance. The Uppsala Architecture Research Team is led by Professors Erik Hagersten and Stefanos Kaxiras, Associate Professor David Black-Schaffer and Assistant Professor Alexandra Jimborean.
Funding and Collaboration
- A dual-consistency cache coherence protocol. In Proc. 29th International Parallel and Distributed Processing Symposium, pp 1119-1128, IEEE Computer Society, Los Alamitos, CA, 2015. (DOI, fulltext).
- StatTask: Reuse distance analysis for task-based applications. In Proc. 7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, pp 1-7, ACM Press, New York, 2015. (DOI).
- A case for resource efficient prefetching in multicores. In Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2014, pp 137-138, IEEE Computer Society, 2014. (DOI).
- A case for resource efficient prefetching in multicores. In Proc. 43rd International Conference on Parallel Processing, pp 101-110, IEEE Computer Society, 2014. (DOI).
- A software based profiling method for obtaining speedup stacks on commodity multi-cores. In Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2014, pp 148-157, IEEE Computer Society, 2014. (DOI).
- A tunable cache for approximate computing. In Proc. 10th International Symposium on Nanoscale Architectures, IEEE International Symposium on Nanoscale Architectures, pp 88-89, IEEE, Piscataway, NJ, 2014. (DOI).
- Dynamic and speculative polyhedral parallelization using compiler-generated skeletons. In International journal of parallel programming, volume 42, number 4, pp 529-545, 2014. (DOI).
- Extending statistical cache models to support detailed pipeline simulators. In Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2014, pp 86-95, IEEE Computer Society, 2014. (DOI).
- Fix the code. Don't tweak the hardware: A new compiler approach to Voltage–Frequency scaling. In Proc. 12th International Symposium on Code Generation and Optimization, pp 262-272, ACM Press, New York, 2014. (URL, fulltext).
- Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed. Technical report / Department of Information Technology, Uppsala University nr 2014-005, 2014. (External link, fulltext).
- Managing power constraints in a single-core scenario through power tokens. In Journal of Supercomputing, volume 68, number 1, pp 414-442, 2014. (DOI).
- Power-Efficient Computer Architectures: Recent Advances. Morgan & Claypool Publishers, 2014. (DOI).
- Resource conscious prefetching for irregular applications in multicores. In Proc. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp 34-43, IEEE, Piscataway, NJ, 2014. (DOI).
- Software-controlled processor stalls for time and energy efficient data locality optimization. In Proc. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp 199-206, IEEE, Piscataway, NJ, 2014. (DOI, fulltext).
- Speculative program parallelization with scalable and decentralized runtime verification. In Runtime Verification, volume 8734 of Lecture Notes in Computer Science, pp 124-139, Springer Berlin/Heidelberg, 2014. (DOI).
- The Direct-to-Data (D2D) Cache: Navigating the cache hierarchy with a single lookup. In Proc. 41st International Symposium on Computer Architecture, pp 133-144, IEEE Press, Piscataway, NJ, 2014. (DOI).
Full UART publications list.
The Uppsala Architecture Research Team was founded in 1999 when Professor Erik Hagersten (PhD from the Royal Institute of Technology) moved back to Sweden from his position as chief server architect at Sun Microsystems. For the first 10 years UART did pioneering work in statistical cache modeling, leading to a successful commercialization of the technology. Professor Stefanos Kaxiras (PhD from Wisconsin) joined the group in 2010, moving from the University of Patras in Greece and bringing extensive experience in power efficiency and coherency. Associate Professor David Black-Schaffer (PhD from Stanford) also joined in 2010, bringing heterogeneous runtime experience from his work on OpenCL at Apple. Assistant Professor Alexandra Jimborean (PhD from University of Strasbourg ) joined in 2012, bringing experience in compile-time and run-time code analysis and optimization. Since then the group has grown to include 12 PhD students and 2 postdocs.