Uppsala Architecture Research Team
StatCC Statistical Cache Contention Modeling
StatCC is a simple and efficient model for estimating the shared cache miss ratios of co-scheduled applications on architectures with a hierarchy of private and shared caches. StatCC leverages the StatStack cache model to estimate the co-scheduled applications´ cache miss ratios from their individual memory reuse distance distributions, and a simple performance model that estimates their CPIs based on the shared cache miss ratios. These methods are combined into a system of equations that explicitly models the CPIs in terms of the shared miss ratios and can be solved to determine both. The result is a fast algorithm with a 2% error across the SPEC CPU2006 benchmark suite compared to a simulated in-order processor and a hierarchy of private and shared caches.
Combining individual core reference streams to determine shared cache contention.
- Fast modeling of shared caches in multicore systems. In Proc. 6th International Conference on High Performance and Embedded Architectures and Compilers, pp 147-157, ACM Press, New York, 2011. (DOI).
- StatCC: a statistical cache contention model. In Proc. 19th International Conference on Parallel Architectures and Compilation Techniques, pp 551-552, ACM Press, New York, 2010. (DOI).
StatCC was selected as the best paper at HiPEAC 2011.