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Department of Information Technology

UART Publications

Refinement and Evaluation of the Elbow Cache

Mathias Spjuth

Master's thesis, UPTEC F-02-033, ISSN 1401-5757, School of Engineering, Uppsala University, Sweden, April 2002.

Abstract

During the last 15-20 years there has been an increasing gap between the bandwidth demands of the modern microprocessor and the performance of the memory sub-system. Memory hierarchies, with nested levels of memory buffers for intermediate caching of data, has been devised as the main solution for this problem. Hardware caching has become of fundamental importance for the overall performance of any modern microcomputer. Consequently, much recent research has been focused on different techniques to improve caching. There are tough demands on a hardware cache. First of all, it needs to be fast to satisfy the CPU's demand for data. It also needs to have good performance in bringing down the total number of data misses. Finally, it must be simple and cheap to implement. In this trade-off between simplicity and performance, cache misses caused by conflicts might become a problem. To mitigate this, different schemes such as victim caches, column-associative caches and skewed-associative caches, have been proposed. This thesis investigates a novel technique to further improve on skewed-associative caching. The technique, dubbed elbow caching, is based on an ability to dynamically move data between alternate positions in the cache. To support this, a new replacement policy based on cache allocation timestamps is suggested. By using trace-driven simulation it is shown that a 2-way elbow cache, using timestamps, has roughly the same miss ratio as a conventional, LRU, 8-way set-associative cache.

Available as PDF (1.3 MB)

BibTeX file entry: Spjuth:2002:apr

Updated  2003-10-15 13:26:20 by Zoran Radovic.