Department of Information Technology

Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management

Speaker

Sally McKee, Chalmers University

Date and Time

Thursday, December 20th, 2012 at 14:00

Location

Polacksbacken, room 1145

Abstract

Power and temperature have joined performance as first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers.
Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging.
Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software.
We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop accurate, application-independent models for several CMPs, and show how they can be used to guide scheduling decisions in power-aware resource managers.

Learning Cache Models by Measurements

Speaker

Jan Reineke, Saarland University

Date and Time

Thursday, December 20th, 2012 at 15:00

Location

Polacksbacken, room 1145

Abstract

Modern microarchitectures employ memory hierarchies involving one or more levels of cache memory to hide the large latency gap between the processor and main memory. Cycle-accurate simulators need to accurately model such memory hierarchies to produce useful results. Similarly, worst-case execution time analyzers require faithful models, both for soundness and precision. Unfortunately, sufficiently precise documentation of the logical organization of the memory hierarchy is seldom available publicly.
We propose an algorithm to automatically model the cache replacement policy by measurements on the actual hardware. We have implemented and applied this algorithm to various popular microarchitectures uncovering a to previously undocumented cache replacement policy in the Intel Atom D525.

Multi-Core Design and Optimization through Mechanistic Analytical Modeling

Speaker

Lieven Eeckhout, Ghent University

Date and Time

Thursday, December 20th, 2012 at 16:00

Location

Polacksbacken, room 1145

Abstract

Analytical modeling is an extremely powerful tool through its ability to generate performance estimates (almost) instantaneously. In this talk, I will describe the interval model, a mechanistic performance model for superscalar cores, after which I will dive into a number of applications for the model. At design-time, we leverage the mechanistic model to raise the level of abstraction in processor simulation, enabling shorter simulator development time and shorter evaluation times. The Sniper simulator is a parallel, hardware-validated multi/many-core simulator built along those principles, and is able to simulate hundreds of cores at high simulation simulation speeds. At run-time, we leverage the model for optimizations through scheduling. We explore how analytical modeling can drive scheduling decisions on simultaneous multi-threading (SMT) cores, as well as homogeneous and heterogeneous multi-cores.

Updated  2012-12-11 08:49:08 by David Black-Schaffer.