Power is Money: Spend it wisely -- Scalable Cores and Caches for Power-Constrained CMPs
David Wood, University of Wisconsin
Date and Time
Tuesday, June 4th, 2013 at 11:15.
Polacksbacken, room 1145
Moore's Law continues to provide exponential growth in transistor density, but the end of Denard Scaling means that a decreasing fraction of transistors can be simultaneously active. As a result, power has become arguably the most critical resource in computer systems design. Moreover, future chip multiprocessor (CMP) systems must support dynamic power budgeting, so that power can be "spent" where it will provide the most (performance) benefit. Future CMPs must provide scalable cores, which scale down to exploit thread-level parallelism when software provides enough threads to run, and scale up to deliver high single-thread performance--via instruction-level and memory-level parallelism--to mitigate sequential bottlenecks and/or to guarantee service-level agreements. Similarly, future CMPs must use scalable caches, which scale up to reduce misses and memory power, or scale down---by reducing capacity and associativity---when power is better spent by the cores.
This talk will discuss the Wisconsin Multifacet project's work on scalable cores and caches to enable power budgeting. WiDGET (Wisconsin Decoupled Grid Execution Tiles) is a scalable core that decouples thread context management from a sea of simple execution units. Forwardflow is an alternative core architecture that dynamically builds an explicit internal dataflow representation from a conventional instruction set architecture, using forward dependence pointers to guide instruction wakeup, selection, and issue. Both WiDGET and Forwardflow provide the flexibility to achieve a particular power-performance target by power-gating unallocated computation resources. Finally, this talk will touch on recent work on dynamically determining the optimal cache configuration for a given workload.
Prof. David A. Wood is a Professor in the Computer Sciences Department at the University of Wisconsin, Madison and has a joint appointment in Electrical and Computer Engineering.
Dr. Wood was named an ACM Fellow (2005) and IEEE Fellow (2004), received the University of Wisconsin's H.I. Romnes Faculty Fellowship (1999), received the National Science Foundation's Presidential Young Investigator award (1991), and earned his Ph.D. in Computer Sciences from the University of California, Berkeley (1990). Dr. Wood is Chair of ACM Special Interest Group on Computer Architecture (SIGARCH), Area Editor (Computer Systems) of ACM Transactions on Modeling and Computer Simulation, is Associate Editor of ACM Transactions on Architecture and Compiler Optimization, served as Program Committee Chairman of ASPLOS-X (2002), and has served on numerous program committees. Dr. Wood is an ACM Fellow, an IEEE Fellow, and a member of the IEEE Computer Society. Dr. Wood has published over 70 technical papers and is an inventor on over a dozen U.S. and International patents.
Dr. Wood co-leads the Wisconsin Multifacet project with Prof. Mark Hill which is exploring techniques for improving the availability, designability, programmability, and performance of commercial multiprocessor and chip multiprocessor servers.