Babak Falsafi, EPFL

Device scaling in processor fabrication technologies along with microarchitectural innovation have led to a tremendous gap between processor and memory performance. While architects have primarily relied on deeper cache hierarchies to reduce this performance gap, the limited capacity in higher cache levels and simple data placement/eviction policies have resulted in diminishing returns for commercial workloads with large memory footprints and adverse access patterns. Moreover, proposals to bridge the gap using runahead execution or large instruction windows do not benefit workloads with little inherent memory-level parallelism such as transaction processing on databases or web servers.

The STeMS (Spatio-Temporal Memory Streaming) project at EPFL is exploring memory system designs that exploit repetitive spatial and temporal correlation among memory accesses and construct memory streams that can be moved and managed together through the memory hierarchy to hide the long access latencies. In this talk, I will present: (a) results from offline trace analysis and cycle-accurate simulation showing that a large fraction of memory accesses in server workloads are spatially and/or temporally correlated, and (b) candidate STeMS architectures to exploit such correlation.

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